1. Field of the Invention
The present invention generally relates to solid state image pickup devices and, more particularly, is directed to a solid state image pickup device including a solid state image pickup element having a pair of output portions which simultaneously derive signals and an external circuit having a pair of circuit systems for processing the signals from the pair of output portions.
2. Description of the Prior Art
Conventional solid state imagers, such as a charge-coupled device (CCD) or the like are generally designed so as to read a signal in the field read-out system. However, in order to increase resolution more, the solid state imager must be designed so as to read whole picture elements (i.e., pixels). If the whole pixels are read, then signals of two horizontal lines must be read during 1H period (H is the horizontal period).
In order to read two horizontal line signals during 1H period, it is proposed to double the frequency of a conventional horizontal transfer clock which drives a horizontal register. This proposal cannot be substantially effected at least in the present condition.
To solve the above problem, another proposal is made, in which a plurality of horizontal registers are provided and signal charges of odd lines and signal charges of even lines are simultaneously horizontally transferred by separate horizontal registers.
FIG. 1 schematically shows a solid state image pickup element of the above-described previously proposed solid state imager.
Referring to FIG. 1, it will be seen that an image unit a is composed of a number of light receiving elements arranged in a two-dimensional, i.e., a matrix shape and vertical shift registers b, b, . . . disposed in accordance with every vertical columns of the light receiving elements so as to transfer the signal charges in the vertical direction. For simplicity, the light receiving elements are not shown and therefore the image unit a is illustrated in FIG. 1 as if it were composed of only the vertical registers b, b, . . .
As shown in FIG. 1, a first horizontal register c is disposed beneath the image unit a and a second horizontal register d is disposed in parallel to the first horizontal register c by a small distance from the first horizontal register c in the under side. A control gate e is disposed between the two horizontal registers c and d so as to control the transfer of signals charges between the first and second horizontal registers c and d. Channel stoppers f are arranged on the semiconductor substrate surface portion at its position corresponding to the underside of the control gate e in the pitch of one pixel and shown by solid rectangle blocks in FIG. 1.
A first output unit g is adapted to derive the signal charges transferred thereto from the first horizontal register c and a second output unit h is adapted to derive signal charges transferred thereto from the second horizontal register d. A first correlation double sampling circuit (CDS circuit) i is adapted to reduce a noise of an output signal from the first output unit g and a second CDS circuit j is adapted to reduce a noise of an output signal from the second output unit h. A first automatic gain control (AGC) amplifier k is adapted to amplify an output signal of the first CDS circuit i and a second AGC amplifier l is adapted to amplify an output signal of the second CDS circuit j. A signal processor circuit m is adapted to derive a luminance signal Y and red and blue color difference signals R-Y and B-Y by sampling respective color signals from the AGC amplifiers k and l.
When the storage of signal charges in the respective light receiving elements is finished, then a signal charge of the first line from the bottom of the image unit a is parallelly transferred to the first horizontal register c and then the signal charge of the first line is transferred to the second horizontal register d by the control gate e. Then, a signal charge of the second line from the bottom of the image unit a is transferred to the first horizontal register c. Thereafter, the signal charges of the first and second lines are simultaneously transferred by the first and second horizontal registers c, d, whereby video signals are simultaneously output to the outside of the solid state imager from the two output units g and h. A series of these operations are repeated at every 1H period.
Japanese Laid-Open Patent Publication No. 62-92587, for example, describes research results of the above solid state imager having two horizontal registers to derive two video signals simultaneously.
Since the solid state image pickup element includes two output units and two circuit systems in the above solid state imager shown in FIG. 1, there is then the problem that a horizontal stripe and a flicker will take place due to a gain difference between the two circuit systems.
Particularly, when the signal is read in the interlace-system, a signal from the same light receiving element (pixel) is transferred by the different horizontal registers c, d at odd and even fields and then output from the different output units g, h. As a consequence, a gain difference between the two circuit systems cannot be neglected. Referring to FIG. 2, let us now describe in detail the above phenomenon such that the signal from the same light receiving element is transferred through the different circuit systems at odd and even fields.
FIG. 2 shows how the signal charges, accumulated in light receiving elements (B0, A0, B1, A1, B2, A2) of one vertical column, are transferred at odd and even fields in a comparing fashion.
As shown in FIG. 2, at the odd field, the light receiving elements B0 and A0, B1 and A1, and B2 and A2 form pairs and the paired signals are simultaneously read by the two horizontal registers c, d. Of the signals of the paired two horizontal lines, signals of the upper light receiving elements A0, A1, A2, . . . are transferred by the first horizontal register c. The flow of the signals transferred by the first horizontal register c is represented by an open arrow in FIG. 2. Of the signals of the paired two horizontal lines, signals of the lower light receiving elements B0, B1, B2, . . . are transferred by the second horizontal register d. The flow of the signals transferred by the second horizontal register d is represented by a solid arrow in FIG. 2. In this case, the open arrow and the solid arrow in FIG. 2 do not mean the difference of signal charge amounts or the like.
At the even field, the light receiving elements A0 and B1, A1 and B2 are paired and the paired signals are simultaneously read by the two horizontal registers c, d. Of the signals of the paired two horizontal lines, the signals of the upper light receiving elements B1, B2, . . . are transferred by the first horizontal register c, while the signals of the lower light receiving elements A0, A1, . . . are transferred by the second horizontal register d.
Accordingly, the signals of the respective light receiving elements are transferred by the different horizontal registers during the odd field or during the even field. More specifically, the signals of the light receiving elements A0, A1, A2, . . . are transferred by the first horizontal register c during the odd field and transferred by the second horizontal register d during the even field. Further, the signals of the light receiving elements B0, B1, B2, . . . are transferred by the second horizontal register d during the odd field and transferred by the first horizontal register c during the even field. As a consequence, the same signal is processed by different circuit systems (channels) during the odd field or during the even field. Accordingly, a gain difference between the two circuit systems causes noises, such as horizontal stripe, flicker and so on to occur.